A module is a Migen class which has mainly two things:

• A table for synchronous fragments
• A table for combinatory fragments

class MyModule(Module):
    def __init__(self):
    led1 = Signal()
    led2 = Signal()
    button = Signal()
 
    self.comb += led1.eq(button)
    self.sync += led2.eq(~led2)

In this example, we have a module which has 2 leds and a button. We also have 2 fragments:

led1.eq(button)
led2.eq(~led2)

As you can see, they are not added to the same table. One goes in the “comb”, the other one to the “sync” Whenever the button is pressed or unpressed, the led1 will switch on or off. This is independent from any clock. But, every time a clock signal occur, led2 will toggle. This is a synchronous statement.

The verilog code generated from Migen with this module is here:

module top(
	output led1,
	output reg led2,
	input button,
	input sys_clk,
	input sys_rst
);
 
assign led1 = button;
always @(posedge sys_clk) begin
	led2 <= (~led2);
	if (sys_rst) begin
		led2 <= 1'd0;
	end
end
endmodule

We will see a bit later how to generate verilog, simulate, or compile with migen. For now we are just interested in the fact that a module can get directly converted into verilog which your favourite fpga vendor tool will compile.