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migen:migen_verilog

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migen:migen_verilog [2018/01/10 18:15]
po
migen:migen_verilog [2018/01/10 18:43] (current)
po
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 ====== Verilog ====== ====== Verilog ======
 +
 One interesting step is to be able to convert a code into verilog, in order to compile it. Althought Migen has it's compiling system included and one does not need to go through verilog in order to do it, we will simply see an example here. One interesting step is to be able to convert a code into verilog, in order to compile it. Althought Migen has it's compiling system included and one does not need to go through verilog in order to do it, we will simply see an example here.
  
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 print(verilog.convert(example,​ {example.hexa,​ example.abcdefg})) print(verilog.convert(example,​ {example.hexa,​ example.abcdefg}))
 </​file>​ </​file>​
 +
 +===== Verilog output =====
  
 <code bash> <code bash>
migen/migen_verilog.txt ยท Last modified: 2018/01/10 18:43 by po