Migen is a Python toolbox for building complex digital hardware. So far, two languages are mainly in use: Verilog and VHDL. Migen brings a new way to write codes for programming FPGA: Fragmented Hardware Description Language (FHDL). It consists of a formal system to describe signals, and combinatorial and synchronous statements operating on them. The formal system itself is low level and close to the synthesizable subset of Verilog, and we then rely on Python algorithms to build complex structures by combining FHDL elements. The FHDL module also contains a back-end to produce synthesizable Verilog, and some structure analysis and manipulation functionality.