pip install git+https://github.com/m-labs/nmigen.git pip install git+https://github.com/m-labs/nmigen-boards.git
(On certain distributions such as Ubuntu, you may have to use pip3
)
For the moment, let's see if your nMigen setup is working. We will get into an explanation of the code in later chapters.
Get the following example:
from nmigen import * from nmigen.back.pysim import * # A simple counter, which increments at every clock cycle. class Counter(Elaboratable): def __init__(self, width): self.v = Signal(width) def elaborate(self, platform): m = Module() m.d.sync += self.v.eq(self.v + 1) return m if __name__ == "__main__": counter = Counter(width=4) # Simply read the count signal and print it. # The output is: # count = 0 # count = 1 # ... with Simulator(counter) as sim: def process(): for i in range(20): print("count =", (yield counter.v)) yield Tick() sim.add_clock(1e-6) sim.add_sync_process(process) sim.run()
You should obtain a counter that goes from 0 to 15 and loops again.
% python counter.py count = 0 count = 1 count = 2 count = 3 count = 4 count = 5 count = 6 count = 7 count = 8 count = 9 count = 10 count = 11 count = 12 count = 13 count = 14 count = 15 count = 0 count = 1 count = 2 count = 3
In the next chapter, we will introduce the basics of the nMigen FHDL.