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nmigen:nmigen_sim_testbench_sync

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nmigen:nmigen_sim_testbench_sync [2019/10/09 18:29]
ramtin
nmigen:nmigen_sim_testbench_sync [2019/10/09 18:29] (current)
ramtin
Line 49: Line 49:
         m.d.comb += self.done.eq(cnt == self.width-1)         m.d.comb += self.done.eq(cnt == self.width-1)
         ​         ​
-        #check if we got start asserted, if so reset the output and counter+        #check if we got 'start' ​asserted, if so reset the output and counter
         with m.If(self.start):​         with m.If(self.start):​
             m.d.sync += [             m.d.sync += [
nmigen/nmigen_sim_testbench_sync.txt ยท Last modified: 2019/10/09 18:29 by ramtin