This JTAG+Serial programmer features a FT4232HL.

Buy it on our shop: Buy JTAG+Serial Programmer Online

This board is setup as follows:

• Channel A: JTAG
• Channel B, C, D: UART

First connect the programmer JTAG pins to your FPGA board using the provided 6-wires jumper. Connect all 6 JTAG pins to your FPGA board: TMS, TDI, TDO, TCK, GND, VCC.

In case your FPGA board uses the JTAG Xilinx’s connector (2×7 pins), you need to use this JTAG Adaptor:

At this step we suppose you have compiled your FPGA bitstream already (.bit file). Read our migen tutorial to learn how to create a bitstream file. Or as an example you can use one of the bitstreams below:

• Led blink for LX16DDR
• Led blink for LX16SDRAM

• http://xc3sprog.sourceforge.net/guide.php

xc3sprog -c ft4232h top.bit

Note: this programming method is not persistent, you will need to reprogram the FPGA every you reset it or power it off.

At power-on, the FPGA reads its bitstream from an SPI Flash memory chip. We use OpenOCD to reprogram the SPI Flash. For this, you will need a SPI .bin file. Read our migen tutorial to learn how to create a SPI .bin file.

You will need the lastest version of openocd, build it from the following github repository:

• https://github.com/ntfreak/openocd

git clone https://github.com/ntfreak/openocd.git
 
cd openocd
 
./bootstrap
./configure
make
 
sudo make install

• https://github.com/jordens/bscan_spi_bitstreams

git clone https://github.com/jordens/bscan_spi_bitstreams.git

These bitstreams are just proxies that will be programmed temporarily on the FPGA and used by openocd to program the SPI Flash with your real .bin file image.

Here is a Xilinx Series-6 configuration file (for Spartan 6)

openocd.cfg

interface ftdi
ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0
ftdi_layout_init 0x0098 0x008b
reset_config none
 
source [find cpld/xilinx-xc6s.cfg]
source [find cpld/jtagspi.cfg]
adapter_khz 10000
 
proc fpga_program {} {
    global _CHIPNAME
    xc6s_program $_CHIPNAME.tap
}

For a Xilinx Series-7 (Artix-7) FPGA, you'd need rather this one that is slightly different.

openocd.cfg

interface ftdi
ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0
ftdi_layout_init 0x0098 0x008b
reset_config none
 
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
adapter_khz 10000
 
proc fpga_program {} {
    global _CHIPNAME
    xc7_program $_CHIPNAME.tap
}

Here we extracted the little migen piece of code, to get it to run standalone. Make sure you are using the right bscan file ! (change it according to your FPGA)

flash.py

#!/usr/bin/env python3
from migen.build.openocd import OpenOCD
 
prog = OpenOCD("openocd.cfg",
        flash_proxy_basename="bscan_spi_xc6slx16.bit")
prog.set_flash_proxy_dir(".")
prog.flash(0x0, "top.bin")

Note: copy the proxy bitstream file bscan_spi_xc6slx16.bit to your working directory or set prog.set_flash_proxy_dir(“.”) accordingly.

python3 flash.py

Run openocd with the above openocd.cfg config file, and enter the following commands in openocd (via telnet):

openocd -f openocd.cfg

In another terminal:

telnet 127.0.0.1 4444
 
init
jtagspi_init 0 bscan_spi_xc6slx16.bit
jtagspi_program top.bin 0x0
fpga_program
exit

# openocd -f flash_screamer.cfg
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 10000 kHz
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
loaded file bscan_spi_xc7a35t.bit to pld device 0 in 0s 218682us
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
Error: Unknown flash device (ID 0x00ffffff)

Ensure you are using the latest version of openocd from the git: #install_openocd

• https://github.com/ntfreak/openocd