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products:lx16sdram [2018/01/10 14:38]
po
products:lx16sdram [2018/01/10 15:16]
po
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 ===== Migen platform file ===== ===== Migen platform file =====
  
-<file python ​lx16ddr.py>+<file python ​lx16sdram.py>
 from migen.build.generic_platform import * from migen.build.generic_platform import *
 from migen.build.xilinx import XilinxPlatform from migen.build.xilinx import XilinxPlatform
Line 42: Line 42:
     ("​user_led",​ 0, Pins("​T9"​),​ IOStandard("​LVCMOS33"​),​ Drive(24), Misc("​SLEW=QUIETIO"​)),​ # D1     ("​user_led",​ 0, Pins("​T9"​),​ IOStandard("​LVCMOS33"​),​ Drive(24), Misc("​SLEW=QUIETIO"​)),​ # D1
     ("​user_led",​ 1, Pins("​R9"​),​ IOStandard("​LVCMOS33"​),​ Drive(24), Misc("​SLEW=QUIETIO"​)),​ # D3     ("​user_led",​ 1, Pins("​R9"​),​ IOStandard("​LVCMOS33"​),​ Drive(24), Misc("​SLEW=QUIETIO"​)),​ # D3
 +
 +    ("​user_btn",​ 0, Pins("​T8"​),​ IOStandard("​LVCMOS33"​)),​ # SW2
 +    ("​user_btn",​ 1, Pins("​R7"​),​ IOStandard("​LVCMOS33"​)),​ # SW3
  
     ("​clk50",​ 0, Pins("​A10"​),​ IOStandard("​LVCMOS33"​)),​     ("​clk50",​ 0, Pins("​A10"​),​ IOStandard("​LVCMOS33"​)),​
Line 62: Line 65:
     ),     ),
  
-    ("ddram", 0+    ("sdram_clock", 0, Pins("H1"), IOStandard("​LVCMOS33"​), ​Misc("SLEW=FAST")), 
-     ​Subsignal("​a"​, Pins("K5 K6 D1 L4 G5 H4 H3 D3 B2 A2 G6 E3 F3 F6 F5"), IOStandard("​SSTL15")), +    ("sdram", ​0
-     ​Subsignal("ba", Pins("​C3 C2 B1"), IOStandard("​SSTL15")), +        Subsignal("​a", Pins("L4 M3 M4 N3 R2 R1 P2 P1", 
-     Subsignal("ras_n", ​Pins("​J6"​),​ IOStandard("​SSTL15"​))+          "N1 M1 L3 L1 K1")), 
-     ​Subsignal("​cas_n", Pins("H5"), IOStandard("​SSTL15"​))+        Subsignal("​ba", Pins("​K3 ​K2")), 
-     Subsignal("we_n", Pins("​C1"​),​ IOStandard("​SSTL15")), +        Subsignal("​cs_n", Pins("​J3"​)),​ 
-     ​Subsignal("​dm", Pins("J4 K3"), IOStandard("​SSTL15")), +        Subsignal("​cke", Pins("J1")), 
-     ​Subsignal("​dq", Pins("K2 K1 J3 J1 F2 F1 G3 G1 L3 L1 M2 M1 P2 P1 R2 R1"), IOStandard("​SSTL15"​),​ Misc("​IN_TERM=UNTUNED_SPLIT_50")), +        Subsignal("​ras_n", Pins("J4")), 
-     ​Subsignal("​dqs_p", Pins("H2 N3"), IOStandard("​DIFF_SSTL15")), +        Subsignal("​cas_n", Pins("H3")), 
-     ​Subsignal("​dqs_n", Pins("H1 N1"), IOStandard("​DIFF_SSTL15")), +        Subsignal("​we_n", Pins("G3")), 
-     ​Subsignal("​clk_p", Pins("E2"), IOStandard("​DIFF_SSTL15")), +        Subsignal("​dq", Pins("A3 A2 B3 B2 C3 C2 D3 E3 G1 F1 F2 E1 E2 D1 C1 B1")), 
-     ​Subsignal("​clk_n", Pins("E1"), IOStandard("​DIFF_SSTL15")), +        Subsignal("​dm", Pins("F3 H2")), 
-     ​Subsignal("​cke", Pins("F4"), IOStandard("​SSTL15")), +        IOStandard("​LVCMOS33"), Misc("​SLEW=FAST"​) 
-     ​Subsignal("​odt", Pins("L5"), IOStandard("​SSTL15")), +    )
-     Subsignal("​reset_n",​ Pins("​E4"​), ​IOStandard("​SSTL15")), +
-     Misc("​SLEW=FAST"​), +
-    ),+
 ] ]
  
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     ("​A",​ "E12 B15 C15 D14 E15 F15 G11 F14 G16 H15 G12 H13 J14 J11 K14 K15 L16 K11 M15 N14 M13 L12 P15 R15 R14 T13 T12"), # U7 1     ("​A",​ "E12 B15 C15 D14 E15 F15 G11 F14 G16 H15 G12 H13 J14 J11 K14 K15 L16 K11 M15 N14 M13 L12 P15 R15 R14 T13 T12"), # U7 1
     ("​B",​ "E13 B16 C16 D16 E16 F16 F12 F13 G14 H16 H11 H14 J16 J12 J13 K16 L14 K12 M16 N16 M14 L13 P16 R16 T15 T14 R12"), # U7 2     ("​B",​ "E13 B16 C16 D16 E16 F16 F12 F13 G14 H16 H11 H14 J16 J12 J13 K16 L14 K12 M16 N16 M14 L13 P16 R16 T15 T14 R12"), # U7 2
-    ("​C",​ "A14 C13 B12 C11 B10 C9 B8 C7 B6 B5 E10 E11 F9 C8 E7 F7 D6 M7 N8 P9 T5 T6 N9 L8 L10 P12 R9"), # U8 1 +    ("​C",​ "A14 C13 B12 C11 B10 C9 B8 C7 B6 B5 E10 E11 F9 C8 E7 F7 D6 P4 P5 M7 N8 P9 T5 T6 N9 M10 P12"), # U8 1 
-    ("​D",​ "B14 A13 A12 A11 A9 A8 A7 A6 A5 A4 C10 F10 D9 D8 E6 C6 N6 P6 L7 T4 R5 T7 M9 M10 P11 M11 T9"​) ​ # U8 2+    ("​D",​ "B14 A13 A12 A11 A9 A8 A7 A6 A5 A4 C10 F10 D9 D8 E6 C6 M6 N5 N6 P6 L7 T4 R5 T7 M9 P11 M11"​) ​ # U8 2
 ] ]
  
Line 99: Line 99:
 ===== Migen Hello World file ===== ===== Migen Hello World file =====
  
-<file python ​blink.py>+<file python ​blinky.py>
 from migen import * from migen import *
  
-import ​lx16ddr+import ​lx16sdram
  
 class Blinky(Module):​ class Blinky(Module):​
Line 117: Line 117:
  
 if __name__ == "​__main__":​ if __name__ == "​__main__":​
-    platform = lx16ddr.Platform()+    platform = lx16sdram.Platform()
     top = Blinky(platform)     top = Blinky(platform)
     platform.build(top)     platform.build(top)
Line 125: Line 125:
  
 <code bash> <code bash>
-python3 ​blink.py+python3 ​blinky.py
 xc3sprog -c ft4232h build/​top.bit xc3sprog -c ft4232h build/​top.bit
 </​code>​ </​code>​
  
 <​html>​ <​html>​
-<script src="​https://​asciinema.org/​a/​9yhG4IE6FujDOrSS0XW0oANmD.js" id="​asciicast-9yhG4IE6FujDOrSS0XW0oANmD" async></​script>​+<script src="​https://​asciinema.org/​a/​kR91XrQy5FmIZoTji1dVWnc5g.js" id="​asciicast-kR91XrQy5FmIZoTji1dVWnc5g" async></​script>​
 </​html>​ </​html>​
  
 {{:​migen:​mov_0107.gif}} {{:​migen:​mov_0107.gif}}
products/lx16sdram.txt · Last modified: 2018/01/10 17:11 by po